Generating a supply voltage entails a number of problems when two voltage sources are available. Managing two voltage sources for generating a supply voltage is more complex and more difficult than generating a supply voltage when only one voltage source is available.
The prior art discloses an embodiment for a circuit for generating a voltage supply, as is illustrated in FIG. 1. In the circuit shown, a choice is made between two external voltage sources and the output voltage VDD is formed using the external supply voltage chosen. To this end, the circuit has a first supply voltage input IN1, to which a first external supply voltage VDDEXT1 is applied, and a second supply voltage input IN2, to which a second external supply voltage VDDEXT2 is applied. The two external supply voltages VDDEXT1 and VDDEXT2 are fed to a respective comparator input of a comparator CMP. At the same time, the two external supply voltages VDDEXT1 and VDDEXT2 are also applied to the inputs of two voltage regulators REG1 and REG2. The two voltage regulators REG1 and REG2 are controlled using an external voltage VDDEXT3 which is applied to a voltage input IN3 of the circuit. At the operating voltage connection BA of the comparator CMP, the external voltage VDDEXT3 simultaneously forms the operating voltage for the comparator CMP and also the operating voltage for an inverter INV that is connected downstream of the latter. The output voltage ENREG1 generated by the comparator CMP is used as an additional control voltage for the first voltage regulator REG1 and, at the same time, as an input voltage for the inverter INV which uses it to form an inverted output voltage ENREG22. This inverted output voltage ENREG22 is used as an additional control voltage for the second voltage regulator REG2. The two outputs of the voltage regulators REG1 and REG2 are connected to one another and form the supply voltage output O of the voltage supply circuit.
In order to ensure that a reverse current does not arise in a system having two supply voltages, it is ensured, in the circuit shown in FIG. 1, that only one of the two voltage sources, and thus only one of the two external supply voltages VDDEXT1 or VDDEXT2, is activated. The other voltage source is deactivated. The voltage source which provides the higher supply voltage is generally chosen. This is because, in the case of the latter voltage source, there is a greater likelihood of the supply voltage provided being greater than the nominal supply voltage VDDnom and thus allowing correct regulation. The comparator CMP decides which of the two external voltage sources provides the higher supply voltage. The comparator CMP therefore compares the first external supply voltage VDDEXT1 with the second external supply voltage VDDEXT2. The higher of the two external supply voltages VDDEXT1 and VDDEXT2 is used to supply the downstream analog components. In this case, the following situations may arise.
1. The first external supply voltage VDDEXT1 is greater than the second external supply voltage VDDEXT2:
In this case, the voltage ENREG1 at the comparator output assumes the value of the external voltage VDDEXT3. In contrast, the inverted voltage ENREG22 at the output of the inverter INV assumes the value zero. The first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal supply voltage VDDnom. In contrast, the second voltage regulator REG2 isolates the second external supply voltage VDDEXT2 from the supply voltage output O because the voltage ENREG22 is 0.
2. The first external supply voltage VDDEXT1 is less than the second external supply voltage VDDEXT2:
In this case, the voltage ENREG1 at the output of the comparator CMP assumes the value zero. The inverted output voltage ENREG2 at the output of the inverter INV is then equal to the external voltage VDDEXT3. The second regulator REG2 regulates the output voltage VDD to the value of the nominal voltage VDDnom. The first voltage regulator isolates the first external supply voltage VDDEXT1 from the supply voltage output O because the voltage ENREG2 is 0.
However, the voltage supply circuit shown in FIG. 1 has a number of disadvantages. If the two external supply voltages VDDEXT1 and VDDEXT2 are greater than the nominal voltage VDDnom, both could be used to regulate the supply voltage VDD. However, only the voltage which is the higher of the two voltages is used. A solution of this type is not optimal in a system in which, although a voltage supply has a high voltage, it cannot provide a high current. That is to say, in the case of such a solution, it is possible to use the voltage source which, although it provides the higher voltage, provides the lower current. Voltage sources which provide a high supply voltage but only a low current may be, for example, magnetic or electric fields. If both voltage sources each provide a supply voltage which is greater than the nominal voltage VDDnom and the voltage source which provides the higher voltage is switched off, the voltage regulator associated with this voltage is also switched off and the other voltage regulator is switched on. In this case, it is difficult to generate a stable supply voltage VDD while changing over between the voltage regulators REG1 and REG2. If the two supply voltage sources provide supply voltages which are of equal magnitude, the two voltage regulators are alternatively switched on and off, which can result in the entire regulating system no longer operating correctly.
As shown in FIG. 2, the prior art discloses another embodiment for supplying voltage. In this embodiment, the first external supply voltage VDDEXT1 is fed to the first input of a comparator CMP1 via the first supply voltage input IN1 and a voltage converter 1. The second external supply voltage VDDEXT2 is routed to the first input of a second comparator CMP2 via the second supply voltage input IN2 and a second voltage converter 2. The second inputs of the first comparator CMP1 and of the second comparator CMP2 are connected to the output of a reference voltage source 3, with the result that a reference voltage VREF is applied to them. As in the case of the embodiment shown in FIG. 1 as well, in the embodiment shown in FIG. 2, the external voltage VDDEXT3 which is applied to the voltage input IN3 is used to control the two voltage regulators REG1 and REG2 and as an operating voltage for the two comparators CMP1 and CMP2. In addition, the external voltage VDDEXT3 is applied to the input of the voltage source 3 which generates the reference voltage VREF.
In the embodiment shown in FIG. 2, the first external supply voltage VDDEXT1 and the second external supply voltage VDDEXT2 are compared with the reference voltage VREF in order to avoid a reverse current. It shall be assumed, for further consideration, that the two voltage converters 1 and 2 multiply the external supply voltages VDDEXT1 and VDDEXT2 by a factor k. It is also assumed that the reference voltage VREF*k is greater than the nominal voltage VDDnom. The following states may occur during operation.
1. The voltage VDDEXT1 is greater than the reference voltage VREF*k and the voltage VDDEXT2 is likewise greater than the reference voltage VREF*k:
In this case, the two voltage regulators REG1 and REG2 regulate the supply voltage VDD to the value of the nominal voltage VDDnom. A reverse current cannot arise in this case since the voltage VDDEXT1 is greater than the reference voltage VREF*k, the latter is, in turn, greater than the nominal voltage VDDnom and the latter is, in turn, greater than or equal to the supply voltage VDD, and, in addition, the voltage VDDEXT2 is greater than the reference voltage VREF*k, the latter is, in turn, greater than the nominal voltage VDDnom and the latter is, in turn, greater than or equal to the supply voltage VDD.
2. The voltage VDDEXT1 is less than the reference voltage VREF*k and the voltage VDDEXT2 is greater than the reference voltage VREF*k:
In this case, the second voltage regulator REG2 regulates the supply voltage VDD to the value of the nominal voltage VDDnom. In contrast, the first voltage regulator REG1 is switched off.
3. The voltage VDDEXT1 is less than the reference voltage VREF*k and the voltage VDDEXT2 is less than the reference voltage VREF*k:
In this case, the two voltage regulators REG1 and REG2 are switched off. The supply voltage VDD is floating.
4. The voltage VDDEXT1 is less than the reference voltage VREF*k and the voltage VDDEXT2 is greater than the reference voltage VREF*k:
In this case, the first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal voltage VDDnom. In contrast, the second voltage regulator REG2 is switched off.
In contrast to the embodiment shown in FIG. 1, most of the disadvantages are avoided in the embodiment of the voltage supply circuit shown in FIG. 2. However, the embodiment shown in FIG. 2 still has the following disadvantages.
The two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 must be matched exactly to one another so that the value k*VREF is greater than the nominal voltage VDDnom. If this is not the case, for example if k*VREF is less than the first external supply voltage VDDEXT1, and the nominal voltage VDDnom is, in turn, less than the second external supply voltage VDDEXT2, both voltage regulators REG1 and REG2 are activated on account of this incorrect matching and a reverse current flows from the second external voltage source, via the second supply voltage input IN2, to the supply voltage output O and from there back to the first external voltage source at the first supply voltage input IN1.
It is frequently the case that the two voltage regulators REG1 and REG2 can be changed over between various nominal voltages VDDnom1, VDDnom2, VDDnom3 etc. In this case, it is necessary for the two voltage converters 1 and 2 to be able to change over between various multiplication factors k1, k2, k3 etc. In this case, it is all the more difficult to exactly match the two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 to one another in the manner already described, to be precise for each pair (VDDnom1, k1), (VDDnom2, k2), (VDDnom3, k3). This results in the circuit requiring more chip area, the power consumption increasing and the complexity of the circuit increasing.